Version Found: v1.04.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)
When synthesizing the AXI Bridge for PCI Express v1.04.a core, the tool issues the following warning messages:
WARNING: [Synth 8-614] signal 'cpl_timer_start_count' is read in the process but is not in the sensitivity list
[ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_04_a/hdl/vhdl/axi_slave_read.vhd:979]
WARNING: [Synth 8-327] inferring latch for variable 'first_word_offset_calc_reg'
[ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_04_a/hdl/vhdl/axi_slave_read.vhd:373]
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
44969 | AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 | N/A | N/A |
AR# 52683 | |
---|---|
Date | 10/31/2012 |
Status | Active |
Type | Known Issues |
IP |