Version Found: v1.04.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)
The AXI Bridge for PCI Express v1.04.a core has C_PCIEBAR2AXIBAR_*_SEC set to '0' by default. C_PCIEBAR2AXIBAR_*_SEC defines the AXI BAR memory space (PCIe BAR_0) (accessible from PCIe) to be either secure or non-secure memory mapped. The recommendation is to set the value of this parameter to '1'.
This is a known issue to be fixed in the next release of the core.
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.