AR# 52773
Virtex-6 FPGA ML605 Evaluation Kit - MIG Reference Design - Valid Data Window Test Fails for Byte Groups 3 and 7
Description
When following the instructions in MIG Creation Design Guide for the ML605 (XTP047),one is directed howto view the valid data window for each byte group.
If one choosesbyte groups 3or 7, this does not generate an error.Does this mean they have an unlimited data eye?
Solution
This is an issue with the data being generated by the traffic generator,the underlying data, not changing on these bytes.The following stepsallow you totest these bytes, as the data in these bytes is changing when set to Hammer mode:
To view the valid data window for byte groups 3 and 7, change theVIO settings in the ChipScope Analyzer after calibration is complete.
1. Set data mode to 3 (Hammer) and address mode to 3 (sequence mode).
2.Disable phase detector.
3. Set enable (bit 25 of VIO4) to 1.
4. Set dbg_inc_dec_sel to 7. This can enable byte 7 delay tap.
5. AssertCPU_RESET.
5. AssertCPU_RESET.
6. Then, add delay tap.
7. After 5 taps, error is asserted, and you can see VIO2 dbg_cpt_tap_cnt[39:35] change from 00110 to 01011. Decreasing the tap can get the same result.
These steps are for Byte 7; use the same sequence of stepsabove for Byte 3.
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Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 34836 | Virtex-6 FPGA ML605 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
| AR# 52773 | |
|---|---|
| Date | 12/12/2012 |
| Status | Active |
| Type | General Article |
| IP |
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| Boards & Kits |
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