AR# 52774


2012.2 Vivado IP Flows - The XDC constraints for a MIG IP are not being read successfully: "[Designutils 20-1277] Could not find cell 'inst'."


I'm getting the following Error when elaborating my design (in which a MIG IP is set as top-level):
[Designutils 20-1277] Could not find cell 'inst'. The XDC file /<proj_dir>/<proj_name>.srcs/sources_1/ip/mig_7series_v1_7_1/mig_7series_v1_7_1/user_design/constraints/mig_7series_v1_7_1.xdc will not be read for this cell.
There is no "inst" in the design or in the XDC.

Where is this name coming from? 


The issue is due to the default instance name of the MIG IP that is set as the top level and the associated XDC constraint that Vivado is attempting to apply to it.

Vivado IP flows expect an IP's top level name (as instantiated within ./synth/<instname>.v/vhd) to be either "inst" or "U0" for Verilog or VHDL designs respectively.

This naming restriction is significant where XDC constraints are applied to an IP within a Vivado design. 

Vivado must scope XDC constraints to a known cell name, here either "inst" (Verilog) or "U0" (VHDL) is expected.

These names were chosen to maintain backwards compatibility with existing CORE Generator IP that may be migrated from an earlier PlanAhead project.

This issue is fixed in Vivado Design Suite 2012.3.
AR# 52774
Date 04/29/2014
Status Archive
Type Known Issues
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