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AR# 52834

2012.3 Vivado Timing Analysis - Why is the MMCM output generated clock value incorrect?

Description


I have an MMCM which takes a 5 ns input clock and generates a 400 MHz (2.5ns) output clock, but I get 2.20e-07 value. This derived clock is incorrect and causes downstream timing errors.

Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes
_0.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clkdiv
Waveform: { 0.15625 1.40625 }
Sources: { system_i/DDR3_SDRAM/DDR3_SDRAM/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrap
per/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV }

Check Type Lib Pin Reference Pin Required Actual Slack Location Pin
Min Period IN_FIFO/WRCLK 2.500 2.500 -2.220e-07 IN_FIFO_X1Y8 system_i/DDR3_SDRAM/DDR3_SDRAM/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrap
per/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo/WRCLK
Low Pulse Width IN_FIFO/WRCLK 1.075 1.250 0.175 IN_FIFO_X1Y8 system_i/DDR3_SDRAM/DDR3_SDRAM/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrap
per/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo/WRCLK



Why is the MMCM output generated clock value incorrect?

Solution

This issue is scheduled to be fixed in the next major release of the Vivado software.
AR# 52834
Date Created 11/07/2012
Last Updated 11/08/2012
Status Active
Type Known Issues
Tools
  • Vivado - 2012.3
  • ??????