AR# 52884


PLBv46PCI v1.04a - Hold Time Violation


If using the PLBv46PCI core, the tool reports the following hold time violation:

Slack (hold path): -1.006ns (requirement - (clock path + clock arrival + uncertainty - data path))
Source: PCI_AD<11> (PAD)
Destination: U_PCI/U_PCI/PCI_CORE_S6_generate.pci_core_s6/XPCI_CORE/XPCI_ADI11 (FF)
Destination Clock: PCI_PCLK_BUFGP rising at 0.000ns
Requirement: 0.000ns
Data Path Delay: 2.857ns (Levels of Logic = 3)(Component delays alone exceeds constraint)
Clock Path Delay: 3.838ns (Levels of Logic = 2)
Clock Uncertainty: 0.025ns


In Spartan-6 devices, it is required that the IDELAY_VALUE for PCI core is set to 83. However, even though the IDELAY_VALUE is set in the UCF, the tool does not apply them because the IODELAY is inferred rather than instantiated.

To work around this issue, perform the following steps:

  1. Implement the design as usual. Let it finish and at the end it should generate an NCD file (the <design_name>.ncd from PAR).
  2. Launch FPGA Editor tool and load the <design_name>.ncd file and the <design_name>.pcf
  3. In the Name Filter, search for *IODELAY*; there should be 36 of them for the PCI core if the design contains other IODELAY for other purposes, you can do search *<core_name>*IODELAY* (replace <core_name> with the name of the PCI module in the design) and that will return the ones just for the PCI core.
  4. Click on the "editmode" button once.
  5. Click on each one of the IODELAY block from the search result you get in step 3 above, and then click the editblock button.
    Note: If the editblock window shows with light gray background, please close this window, and re-do step 4 above until the editblock window shows solid black background. Otherwise it is not editable.
  6. In the editblock window. Click on the "F=" button along the toolbar within this window; this will show the attributes for this block.
    • Change the IDELAY_VALUE in the attribute section to 83.
    • Change the IDELAY_TYPE checkbox to FIXE

      Once done, click the Save button (second button from the right along the toolbar within the window) to save and close the window.
  7. Perform steps 5 and 6 again until all the IODELAY blocks have been changed. Then click save on FPGA editor.

Revision History
11/12/2012 - Initial release

AR# 52884
Date 02/06/2013
Status Active
Type Known Issues
People Also Viewed