UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52934

Can Vivado accept two-dimensional array types as ports?​

Description

When a two-dimensional array is defined as port, my design fails in synthesis with the following error:

ERROR: [Synth 8-2539] port xxx must not be declared to be an array (default settings).

Solution

Two-dimensional array types can be accepted as ports by setting the source files type to SystemVerilog.

Right-click the source file and choose Source Node Properties. Then set Type to "SystemVerilog".

AR# 52934
Date Created 11/14/2012
Last Updated 10/13/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2012.3