My axi_7series_ddrx IP is configured with data width set to 72-bit and ECC enabled.
When working 4 Kbyte transactions, a full write burst is provided to the AXI4 interface.
However, the memory controller still performs Read-Modify-Write (RMW) cycles.
Why does this happen?
When ECC and AXI interface are enabled, RMW cycles cannot be avoid.
AXI allows writes strobed on a per beat basis.
The axi_7series_ddrx IP does not know in advance that all write strobes will be asserted and as a result has no ability to remove the RMW cycles.
| AR# 53009 | |
|---|---|
| Date | 10/15/2014 |
| Status | Active |
| Type | General Article |
| Devices |
|
| Tools |
|