AR# 53020

Description

I have a PlanAhead project with an XPS project instantiated in it. 

When I assign signals to debug in PlanAhead and also in XPS, the tool does not analyze both of the debug signals properly. 

The tool searches for the XPS signals in the ISE and when it does not find them, it returns an error in Implementation.

How can I overcome this error and assign both PlanAhead and ISE signals to debug using ChipScope?

Solution

There are two methods by which you can add signals to ChipScope in PlanAhead and XPS.

1. Inserter flow - where you can directly add the signals to debug after the netlist is generated. 
   You assign this only after the Synthesis runs and a proper netlist is generated.


2. Generator Flow - In this you instantiate the ILA and ICON cores in the design. Then implement it and probe the signals through cChipScope.

When attempting to use an Inserter flow and assign signals to debug in PlanAhead and XPS separately, the tool does not allow it.

This is because the PlanAhead and XPS are using a common debug core which results in a clash. 

The PlanAhead tool searches for the XPS debug signal as given in the chipscope.xml file, and when it does not find it, it will return an error.

Correct Method to analyze the XPS and PlanAhead signals through ChipScope

To overcome this error and properly assign both PlanAhead and XPS signals to debug simultaneously, you can use a Generator flow.

In this flow you need to instantiate ILA cores separately in your XPS and ISE files. 

Then instantiate an ILA core in your XPS top module and connect your debug signals in the XPS to the top module instantiation of the ILA.

Do the same in PlanAhead by instantiating an ILA core for the debug signals.

Then instantiate an ICON core in PlanAhead. 

Connect the outputs of both the ILA signals(from XPS and ISE) to the ICON core in PlanAhead. 

Now you can use ChipScope, which will detect both the XPS and ISE debug cores. 

The diagram below shows how to do this: