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AR# 53031

MIG Virtex-6 DDR3/DDR2 - Fixed Pin-out flow incorrectly allows System Control pins to be allocated in Data or Address/Control bank

Description

The System Control signals (i.e., ERROR and PHY_INIT_DONE) within the MIG Virtex-6 DDR3/DDR2 designs use the LVCMOS25 I/O Standard.

This is not required but is used by default. 

As a result, the MIG Virtex-6 tool only allows these pins to be placed in banks that do not contain Data/Address signals. 

This ensures incompatible I/O Standards are not LOCed within the same bank.

While the default MIG pin-out flow follows this pin guideline, the Fixed Pin-Out mode incorrectly allows System Control pins to be placed in banks that contain Data or Address signals. 

When this happens, Place:864 errors will occur during implementation.

Solution

To work around these errors, either run MIG again and assign the System Control signals to a non-Data/non-Address bank, or change the I/O Standard of the System Control signals to be compatible with the Data/Address signals.
AR# 53031
Date Created 11/20/2012
Last Updated 08/28/2014
Status Active
Type Known Issues
Devices
  • Virtex-6
IP
  • MIG Virtex-6 and Spartan-6