AR# 53053

Description

Version Found: MIG 7 Series v1.7
Version Resolved: MIG 7 Series v1.8

The following read data capture scheme is used by default in the MIG 7 Series QDRII+ generated design. This capture scheme is set using the top-level RTL parameter CPT_CLK_CQ_ONLY=FALSE.

53053_FALSE.jpg

This capture scheme requires the rising edge of CLK and CLKB to maintain a close relationship to ensure read data alignment is captured properly. Read calibration failures have been seen in hardware as a result of the skew differences between PHASER_IN and PHASER_OUT within the same bank being large enough to cause CLKB to capture read data on the wrong edge.

Solution

Calibration failures can occur during Read Calibration Stage 1 if the expected data pattern "0FF0_0F0F" is not seen at the ISERDES outputs. This can be verified using the ChipScope tool by triggering on rdlvl_stg1_start = 1 and monitoring the read data signals and the other Read Stage 1 debug signals referenced in Table 2-20 of the 7 Series FPGAs Memory Interface Solutions User Guide (UG586).

To work around the issue, set parameter CPT_CLK_CQ_ONLY=TRUE in the top-level module or instantiation. CPT_CLK_CQ_ONLY=TRUE will only use CQ to capture read data and uses a local inverter for the CLKB input to the ILOGIC.

Following is a figure of the capture scheme:

53053_TRUE.jpg

Note: Both qdriip_cq_p (CQ) and qdriip_cq_n (CQ#) should be placed on I/O sites, as either CQ or CQ# will actually be used in this capture scheme depending on the MEM_RD_LATENCY parameter value.

The CPT_CLK_CQ_ONLY=TRUE capture scheme removes the PHASER_OUT altogether, which eliminates any skew differences and resolves the data misalignment issue. All MIG 7 Series QDRII+ designs must set the CPT_CLK_CQ_ONLY=TRUE parameter in the top-level module or instantiation as this issue can potentially affect all MIG 7 Series QDRII+ designs. MIG v1.8 and all future releases will use the CPT_CLK_CQ_ONLY=TRUE capture scheme.

Revision History
12/10/2012 - Initial release

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