AR# 53062: System Generator for DSP 14.x - Shared FIFO output data width error in pcore generation with AXI4
AR# 53062
System Generator for DSP 14.x - Shared FIFO output data width error in pcore generation with AXI4
Description
The Shared FIFO block is not recognizing floating point type for the output data width in System Generator for DSP 14.x releases.
In a simple design which has a Shared FIFO, when I tried to generate a pcore, the following error was reported:
standard exception: XNetlistEngine: An exception was raised: com.xilinx.sysgen.netlist.NetlistException: -- An error was encountered while netlisting the shared FIFO named 'CH0.' The FIFO input port width (32) does not match the FIFO output port width (16).
However, the core is configured with output type as floating point, and by default floating point data type is expected to take 32-bit.
Solution
This is a known issue with the Shared FIFO block in System Generator 14.x and a Change Request has been filed.
There is a workaround as follows:
Change the output type to fixed point and select 32.0 in the fixed point precision parameters.