UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - All Programmable
  2. Support
  3. AR# 53068: 3.6 Clocking Wizard - v3.6 Clocking Wizard does not remember the frequency I defined for my CLK1, CLK2, and CLK3 outputs

AR# 53068

3.6 Clocking Wizard - v3.6 Clocking Wizard does not remember the frequency I defined for my CLK1, CLK2, and CLK3 outputs

Description

I generated a Clocking Wizard v3.6 core through CORE Generator with three output clocks. 

When I re-open the CORE Generator project (.cgp file) then attempt to re-customize the IP core, all three output Frequency settings on page 2 are reset to 100MHz.

This was not one of the requested frequencies. 

The tool does remember that I am using three outputs, but I have to re-enter the output frequencies.
 
Is this a known issue?

Solution

This is a known issue, the frequencies should be remembered.

This issue is fixed in the Clocking Wizard v3.6 rev2 available in ISE version 14.4.
AR# 53068
Date 08/12/2014
Status Active
Type Known Issues
Devices
  • Spartan-6
Page Bookmarked