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AR# 53085

2012.3 Vivado - Vivado ignores XDC constraint file when only a device locked license is available

Description

When running a design (i.e. implementing and generating bitstream) with the device locked license (e.g. locked to Kintex-7) in Vivado Design Suite 2012.3, the following critical warnings occur in implementation, which cause errors in bitgen:

Critical Warning:
[Designutils 20-1009] Failed to set Constraints Type for fileset constrs_1 to UCF. UCF constraints are not supported in Vivado.
[Project 1-227] Found UCF constraints while opening checkpoint. UCF constraint support in Vivado is deprecated in the 2012.2 public access release and is no longer available. Please migrate your UCF constraints to XDC-based constraints. Please refer to the Vivado Documentation for more information on migrating UCF constraints.
Bit Generation Error
[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 2 out of 2 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. Problem ports: Button, Led.
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

Solution

This issue has been seen in Vivado Design Suite when a user has a Device Locked or Targeted Design Platform (TDP) License only and has an XDC constraint file in the project. If a Vivado Synthesis or Implementation license (i.e. not a device locked) is available, the same project will complete without any critical warnings or errors and the bitstream can be generated successfully.

This issue is resolved in Vivado Integrated Design Environment 2012.4
AR# 53085
Date Created 12/06/2012
Last Updated 12/06/2012
Status Active
Type Known Issues
Tools
  • Vivado - 2012.3
Boards & Kits
  • Kintex-7 FPGA KC705 Evaluation Kit