We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 53119

2.00.a - ChipScope Artix-7 GTP IBERT - REFCLK0 of PLL0 and PLL1 is always used even though REFCLK1 has been selected in Customize GUI


I select REFCLK1 when I customize IBERT in the GUI, however REFCLK0 is used after I download the .bit file to my boards.

PLL0REFCLKSEL[2:0] or PLL1REFCLKSEL[2:0] is always equal to 3'b001.


This issue only impacts Artix-7 FPGA.

The work-around is to manually change PLL0/1REFCLKSEL[2:0] to 3'b010 in COMMON IBERT Port Settings if you want to use REFCLK1.

With an IBERT bitstream loaded, do the following in ChipScope Analyzer:

1) Open the IBERT console.
2) Select the Port Settings tab, select Common View, and set PLL0REFCLKSEL (or PLL1REFCLKSEL if using PLL1) to 0x2.

On the AC701 board, this will allow use of the second clock on bank 213 (SFP_MGT_CLK1). 


AR# 53119
Date 12/19/2014
Status Active
Type General Article
  • Artix-7
  • ChipScope Pro - 14.3
  • ISE Design Suite - 14.3
  • Vivado Design Suite - 2012.3
Page Bookmarked