I select REFCLK1 when I customize IBERT in the GUI, however REFCLK0 is used after I download the .bit file to my boards.
PLL0REFCLKSEL[2:0] or PLL1REFCLKSEL[2:0] is always equal to 3'b001.
This issue only impacts Artix-7 FPGA.
The work-around is to manually change PLL0/1REFCLKSEL[2:0] to 3'b010 in COMMON IBERT Port Settings if you want to use REFCLK1.
With an IBERT bitstream loaded, do the following in ChipScope Analyzer:
1) Open the IBERT console.
2) Select the Port Settings tab, select Common View, and set PLL0REFCLKSEL (or PLL1REFCLKSEL if using PLL1) to 0x2.
On the AC701 board, this will allow use of the second clock on bank 213 (SFP_MGT_CLK1).