UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 53129

14.3 EDK - Create Import Peripheral - Memory Mapped Burst Compatible Master IPIF Signals

Description

I am using the Create and Import Peripheral (CIP) Wizard to create a custom peripheral with an AXI4 Memory Mapped Burst Compatible interface and Master support.

There are master IPIF signals which do not appear to be documented (for example, ip2bus_mst*).  

Where are these signals documented?

Solution

For more information on these signals, users should refer to DS844, LogiCORE IP AXI Master Burst.

AR# 53129
Date Created 02/14/2013
Last Updated 09/15/2014
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite
  • PlanAhead
  • EDK
  • ISE