The chosen FPGA configuration mode places some constraints on the FPGA application, specifically the I/O voltage allowed on the FPGA's configuration banks.
For example, the SPI or BPI modes leverage third-party flash memory components that are usually 3.3V-only devices (but tolerant of lower voltages).
This requires that the I/O voltage on the bank or banks attached to the memory must comply with the input voltage.
We use LVCMOSxx_12F whatever that bank voltage is set to in order to comply with PROM.
For example for 3.3V PROM, bank voltage is set to Vcco = 3.3V and IOSTANDARD is set to LVCMOS33_12F.
| AR# 53167 | |
|---|---|
| Date | 07/30/2014 |
| Status | Active |
| Type | General Article |
| Devices |
|