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AR# 53242

Vivado - "WARNING: [Designutils 20-195] Net conflicting values (<> vs. <>) on different bits for attribute XLNX_LINE_FILE"

Description

After running synthesis in Vivado, I issue the write_verilog command the following warning occurs:

"WARNING: [Designutils 20-195] Net <Net> conflicting values (<<value>> vs. <<value>>) on different bits for attribute XLNX_LINE_FILE"

What is the XLNX_LINE_FILE attribute?

Where does it come from?

Should I be concerned about this warning?

Solution

The XLNX_LINE_FILE attribute is a tool-generated attribute used for cross-probing between a netlist or internal design object and an RTL source file.

This warning is most likely to occur if a project includes an encrypted source file with a XLNX_LINE_FILE attribute already embedded.

In this event, an attempt to cross-probe from this particular net or object will take you to the location of the last XLNX_LINE_FILE attribute encountered for the object, possibly directing you to the wrong references in the RTL.

If you do not intend to utilize cross-probing, this warning can be safely ignored.

AR# 53242
Date Created 12/07/2012
Last Updated 12/07/2012
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado