If multiple DDR2/DDR3 are generated within the MIG 7 Series GUI with "NO BUFFER" selected for sys_clk or ref_clk, c0_mmcm_clk will be connected to all clock inputs of the PLL in the user design top module.
Users should modify the code manually to set up the expected clocking architecture. If NO BUFFER is selected, no IBUFG or IBUFGDS will be generated. The user should modify the clocking according to (Xilinx Answer 40603).
Revision History
12/3/2012 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 40603 | MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines | N/A | N/A |
| 45195 | MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions | N/A | N/A |
| AR# 53249 | |
|---|---|
| Date | 09/30/2013 |
| Status | Active |
| Type | General Article |
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