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AR# 53251

7 Series Integrated Block for PCI Express - v1.8 (ISE 14.4) - Setup timing violations on paths between ../pcie_block_i (CPU) and [../bram36_dp_bl.bram36_tdp_bl (RAM)]/ ] / [../sdp_bl.ramb36_dp_bl.ram36_bl (RAM)]

Description

Version Found: v1.8
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

When implementing a design with the 7 Series Integrated Block for PCI Express - v1.8 core, the tool reports setup timing violations for the following paths:

Slack (hold path):      -0.084ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cgator_wrapper_i/rport/pcie_top_i/pcie_7x_i/pcie_block_i (CPU)
  Destination:          cgator_wrapper_i/rport/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_sdp.ramb36sdp/bram36_dp_bl.bram36_tdp_bl (RAM)

 

Slack (hold path):      -0.075ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cgator_wrapper_i/rport/pcie_top_i/pcie_7x_i/pcie_block_i (CPU)
  Destination:          cgator_wrapper_i/rport/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_sdp.ramb36sdp/sdp_bl.ramb36_dp_bl.ram36_bl (RAM)


Solution

This is a known issue to be fixed in a future release of the core.

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

AR# 53251
Date Created 12/17/2012
Last Updated 10/16/2014
Status Active
Type Known Issues
IP
  • 7 Series Integrated Block for PCI Express (PCIe)