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AR# 53266

Vivado Implementation - How do you add an output port for debug purposes after implementation?


Is it possible to add a Debug port in Vivado post implementation, similar to adding a probe in FPGA Editor without modifying the design?

If so, how can this be done in a Vivado design?


Probes can be added in the Vivado design tools via Tcl scripting.

The following Tcl script allows you to create a test port defining the I/O Standard, the port location, and the net to probe:

addProbe {signal pin IOStandard name}
  • signal: full name of the signal to probe
  • pin: location of the output port
  • IOStandard: output Standard
  • name: output port name.

The script creates a port with the given name connected via an OBUF to the specified internal net.

Once the script is loaded in the Vivado tools, the procedure can be called from the Tcl console like any Vivado command:

addProbe <>/data_internal K17 LVCMOS18 my_new_port
Since 2014.X the command to call loaded scripts in Vivado is:
apps::addProbe <>/<>/internal_signal C19 LVCMOS25 new_port

Note 1: There may be problems if the probing net has some particular properties attached, for instance "dont_touch." 

In that case, this option must be disabled before adding the test-port or the tool will issue a warning and the port will not be connected.

Note 2: For 2013.3 and beyond, use the script named addprobe_2013_3.tcl.

Useful tip: This script can be added to the Vivado tool interface as a button which will then load the Tcl file. 

To use this option, go to Tools -> Custom Commands -> Customized commands.


Associated Attachments

Name File Size File Type
addProbe.tcl 1 KB TCL
addprobe_2013_3.tcl 2 KB TCL
AR# 53266
Date 03/05/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite