Version Found: v1.7
Version Resolved: See (Xilinx Answer 45195)
Designs generated using MIG 7 Series with the settings" System Clock = No Buffer" and "Reference Clock = Use System Clock" fail during synthesis with the following messages:
This is expected behavior when "System Clock = No Buffer" and "Reference Clock = Use System Clock" are chosen.
MIG will generate a design without I/O or buffers for the System Clock and Reference Clock.
If the System and Reference Clocks are not manually declared, Synthesis will fail because the mig_7series_v1_7_iodelay_ctrl module needs the reference clocks to be supplied.
If selecting "System Clock = No Buffer" and "Reference Clock = Use System Clock" is required, then you must declare the sys_clk_p/n and clk_ref_p/n signals in the mig_7series_v1_7 module.
Starting with MIG 1.9, this information will be added to the 7 Series FPGAs Memory Interface Solutions User Guide (UG586).