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AR# 53331

LogiCORE IP AXI Video Direct Memory Access v5.03.a - Genlock Source bit in control register not set by driver

Description

I am trying to configure the AXI VDMA using the provided driver. I call the XAxiVdma_GenLockSourceSelect() function to set the genlock source for the MM2S side. In my hardware, I set the MM2S to genlock slave and I am using internal genlock mode, as recommended. However, reading back the MM2S Control Register, the genlock source bit is still set to 0, indicating external genlock. This results in choppy video on the screen. What is going on?

Solution

This is a known issue with this version of the driver (driver version v4.01.a). The workaround is to not call the XAxiVdma_GenLockSourceSelect() function and directly write the MM2S control register instead. Simply use the utilities in xil_io.h to mask in the genlock_src bit.

int mm2s_cr;
mm2s_cr = Xil_In32(BaseAddress+XAXIVDMA_TX_OFFSET+XAXIVDMA_CR_OFFSET);
Xil_Out32(BaseAddress+XAXIVDMA_TX_OFFSET+XAXIVDMA_CR_OFFSET, mm2s_cr | XAXIVDMA_CR_GENLCK_SRC_MASK);

This will be fixed in the next version of the driver (driver version v4.03.a)

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47654 AXI Video Direct Memory Access (VDMA) - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
55221 LogiCORE IP AXI Video Direct Memory Access - Low frame rate/choppy video N/A N/A
AR# 53331
Date Created 12/05/2012
Last Updated 09/16/2013
Status Active
Type General Article
IP
  • Interconnect Infrastructure
  • AXI Video DMA