Description

Version Found: v1.8a
Version Resolved: See (Xilinx Answer 45195)

The Vivado tool includes an "Open IP Example Design" feature that allows a Vivado project to be automatically created with the IP's example design. This flow is supported with MIG 7 Series. There are potential issues when using this feature in the 2012.4 tool. This answer record details the potential issues and associated work-arounds.

Solution

Debug Signals Enabled

If the Debug Signals are enabled in the MIG 7 Series tool, ChipScope cores should be added into the Example Design Vivado project automatically. In the 2012.4 tool, the ChipScope cores are not added which causes a "black box not found" error to be issued.

Work-around:  Manually add the ChipScope cores into the Example Design Vivado project. In the Vivado Tcl console, the following commands can be used to manually add the ChipScope cores:

set_property used_in_synthesis false [ get_file ddr_icon.xdc] 
set _xcopath  [ get_property IP_DIR [ get_ips my_mig ]]/[get_property name [ get_ips my_mig ]]/example_design/par/;
Note: "my_mig" is the instance name. Replace as per the instance name in the target project.
import_ip -file $_xcopath/ddr_icon_cg.xco -name ddr_icon ;
import_ip -file $_xcopath/ddr_ila_basic_cg.xco -name ddr_ila_basic  ;
import_ip -file $_xcopath/ddr_ila_wrpath_cg.xco -name ddr_ila_wrpath ;
import_ip -file $_xcopath/ddr_ila_rdpath_cg.xco -name ddr_ila_rdpath ;
import_ip -file $_xcopath/ddr_vio_sync_async_out72_cg.xco -name ddr_vio_sync_async_out72 ;
import_ip -file $_xcopath/ddr_vio_async_in_sync_out_cg.xco -name  ddr_vio_async_in_sync_out ;

Critical Warnings

If implementing the Example Design Vivado project, critical warnings might be issued for the following pins. Users can either work around the critical warnings by executing a tcl command similar to the following (replacing my_mig with the project's instance name) in the Tcl console:

     set_property IS_ENABLED 0 [get_files -of [get_property IP_FILE [  get_ips my_mig]] */[get_property name [get_ips my_mig]].xdc]

Or, users can comment out the constraints related to the specific pin causing the critical warning as shown below:

DDR3/DDR2 Design

The "sys_rst" pin in the user design xdc will cause critical warnings because an IBUF gets inserted between the sys_rst pin to the top level port.

Work-around:  Comment out the sys_rst LOC and IOSTANDARD constraints in the user_xdc at located at:

<path of project..my_mig>/example_project/my_mig_example/my_mig_example.srcs/sources_1/ip/my_mig/my_mig/user_design/constraints
       #set_property IOSTANDARD LVCMOS25 [get_ports {sys_rst}]
       #set_property LOC <AD29> [get_ports {sys_rst}]

In MIG v1.9, these critical warnings will be resolved with the default MIG design (no modifications required) by properly inserting the IBUF and placement constraints based on whether a sys_rst pin is selected through the MIG 7 Series tool.

QDRII+ Multi-Controller Design

The "qdriip_dll_off_n" pin in user design xdc issues critical warnings because an OBUF gets inserted between pin and pad.

Work-around:  Comment out the C0_qdriip_dll_off_n constraints in user design xdc ( for Controller 0) at:

<path of project..my_mig>/example_project/my_mig_example/my_mig_example.srcs/sources_1/ip/my_mig/my_mig/user_design/constraints
       #set_property SLEW FAST [get_ports {c0_qdriip_dll_off_n}]
       #set_property IOSTANDARD HSTL_I [get_ports {c0_qdriip_dll_off_n}]
       #set_property LOC N34 [get_ports {c0_qdriip_dll_off_n}]