AR# 53420

Design Advisory for MIG 7 Series DDR3 - Required calibration patch for v1.7 and v1.8


Version Found: MIG 7 Series v1.7
Version Resolved: See (Xilinx Answer 45195)

New calibration updates are required for MIG 7 Series DDR3 designs due to potential calibration failures across process variation or continuous resets. This answer record details the calibration updates and includes links to patches for both MIG 7 Series v1.7 and v1.8 designs. Moving to v1.8 is recommended but not required as long as the v1.7 patch from this answer record is applied.


OCLKDELAY Calibration Update

Background: The v1.7 OCLKDELAY calibration algorithm used an initial Phaser_OUT tap value of 30. This provided an approximate 90 degree shift starting point before edge detection. This allowed the algorithm to place the write DQS in the rise window between 90 and 180 degrees. The algorithm relied on edge detection only.

The problem found with this algorithm is the 90-180 degree window is not large enough across process variation.

Potential Failure Mechanism: Calibration failures (specifically write calibration failures) occur across process variation where the 90-180 degree window does not cover the DQS starting point.

Fix: In the new OCLKDELAY calibration algorithm, the initial Phaser_OUT tap value changed from 30 taps to a frequency dependent value and the initial sampling range expanded to 90 - 225 degrees. Additionally, pattern detection was added as an enhancement beyond the pre-existing edge detection.

This new algorithm covers ALL process variation for ALL revisions of 7 series silicon. Updates are made to the ddr_phy_oclkdelay_cal and ddr_mc_phy_wrapper modules. The ZIP files at the end of this answer record contain the updated rtl with instructions for how to include the files in the generated MIG 7 Series v1.7 or v1.8 designs.

PRBS Calibration Update

Background: The MIG 7 Series v1.7 PRBS Read Leveling RTL missed a corner case where specifically the signals "phy_if_empty" and "reseed_prbs_r" are simultaneously asserted. This caused the compare data generated by the ddr_prbs_gen.v module to be out of sync with the read data coming back from the DRAM.

Potential Failure Mode: When this corner case was hit, the final PRBS tap value was incorrect causing a bit time shift to be seen in the received data post calibration. This corner case failure is seen on multiple consecutive resets (i.e., 500-1000 resets).

Fix: MIG 7 Series v1.8 designs include the RTL updates by default. The v1.7 patch linked below includes the updated rtl along with instructions for how to include the files in the generated MIG 7 Series v1.7 designs.

Write Leveling Calibration Update

Background: On some resets, the write leveling algorithm aligns DQS to the negative edge of CK. When this happens, the MIG v1.8 and prior write leveling algorithm did not have a long enough 0 detection period (7 zeros), causing a 1 found in a noise region to be considered a 0 to 1 edge transition and incorrect completion of the write leveling.

Potential Failure Mode: This false edge detection may cause tDQSS violations on writes issued to the DRAM, and, therefore, write data errors post calibration.

Fix: The write leveling algorithm has been updated to detect a longer low period (fourteen 0s instead of seven 0s) to prevent the detection of a false 0 to 1 transition around the falling edge of CK. This fix includes updates to the ddr_phy_wrlvl module which is included in both the v1.7 and v1.8 patches below.

Note: To apply the patch for EDK and MPMC designs, replace the files located in $XILINX$\EDK\hw\XilinxProcessorIPLib\pcores\axi_7series_ddrx_v1_06_a\hdl\verilog with the ones provided in the patch.


Associated Attachments

Name File Size File Type 32 KB ZIP 43 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
53962 Design Advisory Master Answer Record for Virtex-7 FPGA VC707 Evaluation Kit N/A N/A
AR# 53420
Date 04/10/2013
Status Active
Type Design Advisory