Version Found: 1.8.a
Version Resolved: See (Xilinx Answer 45195)
When generating a DDR2 MIG 7 Series design through the native Vivado flow, the simulation show X's on bidirectional signals in XSIM even though the same designs pass in other simulators such as ModelSim and ISIM.
This is due to an issue with XSIM as described in this answer record.
Background: The example_design/sim/sim_tb_top.v testbench includes the following rtl:
in gen_mem_extrabits
.dm_rdqs ({ddr2_dm_sdram[DM_WIDTH-1],ddr2_dm_sdram[DM_WIDTH-1]}),
.dq ({ddr2_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)], ddr2_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr2_dqs_p_sdram[DQS_WIDTH-1], ddr2_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr2_dqs_n_sdram[DQS_WIDTH-1], ddr2_dqs_n_sdram[DQS_WIDTH-1]}),
XSIM does not currently support this type of construct causing X to be driven on bi-directional signals.
Work-around: Use ISIM or ModelSim to work around this behavior.
| AR# 53431 | |
|---|---|
| Date | 08/14/2014 |
| Status | Active |
| Type | Known Issues |
| Devices |
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| IP |
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