AR# 53435


MIG 7 Series DDR3/DDR2 - Timing violations may be seen in 2:1 designs running around 533MHz within u_ddr_mc_phy


Version Found: 1.8
Version Resolved: (Xilinx Answer 45195)

Timing violations similar to the following can be seen in MIG 7 Series DDR3/DDR2 2:1 designs running at frequencies around the maximum supported frequency of 533 MHz:

Slack (VIOLATED) :        -0.091ns
  Source:                 u_mig_7series_v1_8/u_mig_7series_v1_8_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/
                            (rising edge-triggered cell FDSE clocked by clk_pll_i  {rise@0.000ns fall@1.875ns period=3.750ns})
  Destination:            u_mig_7series_v1_8/u_mig_7series_v1_8_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/


To work around these timing failures, there is an optional parameter within the mig_7series_v1_8_ddr_phy_top.v module that can be enabled:

     parameter RD_PATH_REG     = 0              // optional registers in the read path
                                                                               // to MC for timing improvement.
                                                                               // =1 enabled, = 0 disabled

AR# 53435
Date 08/14/2014
Status Active
Type Known Issues
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