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AR# 53439

MIG 7 Series RLDRAM II - Read Leveling Stage 2 calibration can fail with some configurations


Version Found: v1.8
Version Resolved and other Known Issues: See (Xilinx Answer 45195)

When implementing the MIG 7 Series RLDRAM II v1.8/v1.8a design, Read Leveling Stage 2 can fail when configured with the following:


T1 and T2 byte lanes are used for Data


When data byte groups are allocated to T1 and T2 byte lanes of a bank, the data bits and read strobes will occupy all available pins in the T1 and T2 byte lanes, which forces the write strobes to be placed on either T3 or T0. When this occurs, MIG incorrectly defines the DATA_CTL_B# pinout parameter to 4'b0110, which will cause Read Leveling Stage 2 to fail during calibration. To work around the issue, redefine the DATA_CTL_B# pinout parameter based on whether or not the write strobes (DK) were placed in T3 or T0 as follows:

If DK is placed in T3 set:

DATA_CTL_B#           = 4'b1110;

If DK is placed in T0 set:

DATA_CTL_B#           = 4'b0111;

Refer to UG586 for more details on the pinout parameters.

Revision History
12/18/2012 - Initial release

AR# 53439
Date 03/27/2013
Status Active
Type Known Issues
  • Kintex-7
  • Virtex-7
  • MIG 7 Series