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AR# 53466

Spartan-6 FPGA Triple Rate SDI v1.0 - How do I create constraints for the Spartan-6 Triple Rate SDI core?

Description

I am trying to use the Spartan-6 FPGA Triple Rate SDI v1.0 core in my design, but I have found a syntax error in the .ucf file provided with this core. How do I correct this and create proper constraints for the Spartan-6 Triple Rate SDI core?

Here is the multi cycle path section in the UCF:

NET */FRM/dly_reg* TNM = frm_in;
TIMEGRP frm_ffs = FFS ("*/FRM/*") frm_out;
TIMESPEC TS_rx1_frm_sd = FROM frm_in THRU frm_sd_thru TO frm_ffs 54 MHz;
TIMEGRP test_dest = FFS (*/FRM/offset_reg*); TIMESPEC TS_test = THRU test_thru TO test_dest 54 MHz; # These constraints relax the timing on the DRU, used for SD-SDI This path # only has to run at SD-SDI clock rate of 74.25 MHz. # TIMEGRP dru_ffs = FFS (*/DRU*/*); TIMESPEC TS_dru_ffs = TO dru_ffs 74.25 MHz;

However, frm_sd_thru and test_thru are not defined anywhere in the UCF.

Solution

This is a known issue with this version of the core.

To work around this problem, you can pull the constraints from the XAPP1076 reference design.

For a detailed list of LogiCORE IP Spartan-6 FPGA Triple-Rate SDI Release Notes and Known Issues, see (Xilinx Answer 42805).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42805 LogiCORE IP Spartan-6 FPGA Triple-Rate SDI (Serial Digital Interface) - Release Notes and Known Issues N/A N/A
AR# 53466
Date Created 12/12/2012
Last Updated 12/18/2013
Status Active
Type General Article
Devices
  • Spartan-6 LXT
IP
  • Spartan-6 FPGA Triple-Rate SDI