Description

I am using IODELAY and IDELAYCTRL elements in my design and receive the following message:

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
   design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
   To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
     Unroutable      signal: top/signal_1<1>      pin:  top/xyz/idelayctrl_inst0_MapLib_replicate6/REFCLK
     Unroutable      signal: top/signal_2<1>      pin:  top/xyz/idelayctrl_inst0_MapLib_replicate7/REFCLK    

Why is this happening?

Solution

This issue occurs because the IDELAYCTRL should be driven by a BUFG instead of a BUFR, as stated in the Select IO Users Guide for Virtex 6:

"REFCLK - Reference Clock
The reference clock (REFCLK) provides a time reference to IDELAYCTRL to calibrate all IODELAYE1 modules in the same region. 

This clock must be driven by a global clockbuffer (BUFGCTRL). 

REFCLK must be FIDELAYCTRL_REF the specified ppm tolerance (IDELAYCTRL_REF_PRECISION) to guarantee a specified IODELAYE1 resolution (TIDELAYRESOLUTION). 

REFCLK can be supplied directly from a user-supplied source or the MMCM and must be routed on a global clock buffer."