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AR# 53511

AXI Bridge for PCI Express v1.05.a [Vivado 2012.3] - [IP_Flow 19_1710] Problem delivering 'Verilog Synthesis' files for IP 'axi_pcie_v1_05_a_0'

Description

Version Found: v1.05.a
Version Resolved and other Known Issues
: See (Xilinx Answer 44969)

When generating AXI Bridge for PCI Express v1.05.a core in Vivado Design Suite 2012.3, the tool gives the following error message:

[IP_FLOW 19-167] Failed to deliver one or more file(s).
[IP_FLOW 19-1710] Problem delivering 'Verilog Synthesis' files for IP 'axi_pcie_v1_05_a_0'.
[IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate 'Verilog Synthesis' output product for IP 'axi_pcie_v1_05_a_0'':

Solution

This is a known issue to be fixed in the next release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
12/17/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 53511
Date Created 12/18/2012
Last Updated 08/26/2013
Status Active
Type General Article
Tools
  • EDK
  • Vivado Design Suite
IP
  • AXI PCI Express (PCIe)