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AR# 53550

7-series Integrated Block Wrapper for PCI Express v1.7 - 128-bit user interface with 64-bit BAR simulation is not working - malformed packet sent by the Root Port Simulation Model (DSPORT)


Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

When simulating the Endpoint core that was set-up with 128-bit user interface and 64-bit BAR, the simulation will fail because malformed packet was sent from the Root Port simulation model (DSPORT). Cores with 32-bit BAR only or with 64-bit user interface are NOT affected.

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


The issue was found in the pci_exp_usrapp_tx module under task tsk_memory_write_64:

                        if (ep_)

                            trn_terrfwd_n  <= #(Tcq) 0;

                        trn_tsrc_rdy_n     <= #(Tcq) 1;


                        case ((_len - 1) % 4)

                          1 : trn_trem_n   <= #(Tcq) 2'b11;  // D0---------

                          2 : trn_trem_n   <= #(Tcq) 2'b10;  // D0-D1------

                          3 : trn_trem_n   <= #(Tcq) 2'b01;  // D0-D1-D2---

                          0 : trn_trem_n   <= #(Tcq) 2'b00;  // D0-D1-D2-D3

The correct RTL should be:

                        if (ep_)

                            trn_terrfwd_n  <= #(Tcq) 0;

                        trn_tsrc_rdy_n     <= #(Tcq) 0;


                        case ((_len - 1) % 4)

                          0 : trn_trem_n   <= #(Tcq) 2'b11;  // D0---------

                          1 : trn_trem_n   <= #(Tcq) 2'b10;  // D0-D1------

                          2 : trn_trem_n   <= #(Tcq) 2'b01;  // D0-D1-D2---

                          3 : trn_trem_n   <= #(Tcq) 2'b00;  // D0-D1-D2-D3

Revision History:
12/17/2012 - Initial Release

Linked Answer Records

Master Answer Records

AR# 53550
Date 06/21/2013
Status Active
Type Known Issues
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