This answer record covers the RX reset sequence requirements for the Artix-7 GTP Transceiver Production Silicon.
The required sequences to follow for issuing GTRXRESET, RXPMARESET, or RXRATE in the Artix-7 GTP Production Transceivers are documented below. These reset sequences can be also used on General ES silicon but are not required.
These sequences are implemented in the wrapper generated by 7 Series FPGAs Transceivers Wizard v2.5 in the "ISE 14.4.1 Device Pack" or ISE 14.5/Vivado 2013.1 tool version. The reset sequences are added to v1.4 of the 7 Series FPGA GTP Transceiver User Guide (UG482). Note, special care is needed in simulation. Please see the "Additional Requirements for Simulation" section below.
In these sequences, "user_*" denotes user input. This signal was previously connected directly to the GT primitive. It will now trigger an alternative reset sequence as described below.
"gt_*" denotes connection to GT primitive. The following diagram indicates where this new sequence fits in.
"DRP wr" denotes the function of performing a DRP write to address 9'h011. The exact DRP transaction is not shown.
1) GTRXRESET:
The following reset sequence must be followed when the user wants to perform GTRXRESET.
Steps:
Notes:
2) RXPMARESET:
The following reset sequence must be followed when the user wants to perform RXPMARESET.
Steps:
Note: Make sure gt_RXPMARESET is output of a register.
3) RXRATE:
The following sequence must be followed when the user wants to trigger RX rate change via RXRATE.
Note: The sequence above will only simulate properly if SIM_GTRESET_SPEEDUP is set to FALSE. If SIM_GTRESET_SPEEDUP is set to TRUE, the above sequence must be bypassed. See the "Additional Requirements for Simulation" below.
GTP Attribute:
In addition to the required sequences above, the following attribute must be set correctly:
PMA_RSV2 = 32h'00002040.
Additional Requirements for Simulation
While these sequences are implemented in the wrapper generated by the 7 Series FPGAs Transceivers Wizard for proper hardware operation, users might see in simulation that the RXOUTCLK, RXUSRCLK, and RXUSRCLK2 run at the incorrect clock rates.
For example, the clock rates are the GT rate divided by 16 instead of the correct divide rate of 20 for a configuration with 8b10b decoder enabled and an internal data width of 20.
To work around/bypass this behavior in simulation and generate the correct clock rates, step through the following:
After these changes, the proper clock rates will be seen in simulation within ~20us of reset.
Revision History
02/14/2017 | Added Additional Requirements for Simulation |
04/12/2013 | Updated the user guide version with the reset sequence |
01/31/2013 | Initial release |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
51456 | Design Advisory Master Answer Record for Artix-7 FPGA | N/A | N/A |
47852 | 7 Series FPGAs GTP Transceivers - Known Issues and Answer Record List | N/A | N/A |
54473 | LogiCORE IP CPRI Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
54232 | 7 Series Integrated Block Wrapper for PCI Express v1.8 (ISE 14.4/2012.4) - How to generate the core for Artix-7 Production Silicon | N/A | N/A |
55445 | RXAUI v2.4, 7 Series - Required GTP/GTX and GTH transceiver updates | N/A | N/A |
55446 | XAUI v10.4 - 7 Series - Required GTP/GTX and GTH transceiver updates | N/A | N/A |
62770 | Design Advisory for 7-Series Integrated Block for PCI Express / AXI Bridge for PCI Express (Vivado 2013.3 - Vivado 2014.3) - Link training issue with GTP devices | N/A | N/A |
54249 | IP Release Notes and Known Issues for LogiCORE RXAUI for Vivado 2013.1 and newer tool versions | N/A | N/A |
AR# 53561 | |
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Date | 02/17/2017 |
Status | Active |
Type | Design Advisory |
Devices |