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AR# 5358

COREGEN, VHDL: Output still available from VHDL behavioral model for area-optimized multiplier when CE is deactivated


Keywords: coregen, vhdl, multiplier, output, ce

Urgency: standard

General Description:
The Area Optimized Multiplier with Coregen are created with a CE pin. According to the datasheet,
this pin should stop all activity within the block (i.e., data should not flow
between the pipeline stages) when it is deasserted. However, when doing a behavioral simulation
with the VHDL model, the CE pin only inhibits data from flowing into the first pipeline stage, but not
between internal stages, and an output is still observed on the multiplier.


The problem is in the coding of the VHDL model for the multiplier on line 112:

elsif (c'event and rat(c)='1' and rat(c'last_value)='0')

To fix the problem, change line 112 of the COREGEN VHDL model to
include an additional constraint on the CE input:

elsif (c'event and rat(c)='1' and rat(c'last_value)='0' and rat(ce) /='0')

This problem was fixed in the version of CORE Generator shipped with
the A2.1i and F2.1i releases.
AR# 5358
Date 03/15/2000
Status Archive
Type General Article
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