AR# 53635


Where to find the library cell B_IOSERDESE2?


When using a 3rd party simulation tool errors similar to the following may be encountered:

Error-[URMI] Unresolved modules
/global/snps_apps5/xilinx_14.4/14.4/ISE_DS/ISE/verilog/src/unisims/OSERDESE2.v, 250
"B_OSERDESE2 #(.DATA_RATE_OQ(DATA_RATE_OQ), .DATA_RATE_TQ(DATA_RATE_TQ), .DATA_WIDTH(DATA_WIDTH), .INIT_OQ(INIT_OQ), .INIT_TQ(INIT_TQ), .SERDES_MODE(SERDES_MODE), .SRVAL_OQ(SRVAL_OQ), .SRVAL_TQ(SRVAL_TQ), .TBYTE_CTL(TBYTE_CTL), .TBYTE_SRC(TBYTE_SRC), .TRISTATE_WIDTH(TRISTATE_WIDTH)) B_OSERDESE2_INST( .OFB (delay_OFB),  .OQ (delay_OQ),  .SHIFTOUT1 (delay_SHIFTOUT1),  .SHIFTOUT2 (delay_SHIFTOUT2),  .TBYTEOUT (delay_TBYTEOUT),  .TFB (delay_TFB),  .TQ (delay_TQ),  .CLK (delay_CLK),  .CLKDIV (delay_CLKDIV),  .D1 (delay_D1),  .D2 (delay_D2),  .D3 (delay_D3),  .D4 (delay_D4),  .D5 (delay_D5),  .D6 (delay_D6),  .D7 (delay_D7),  .D8 (delay_D8),  .OCE (delay_OCE),  .RST (delay_RST),  .SHIFTIN1 (delay_SHIFTIN1),  .SHIFTIN2 (delay_SHIFTIN2),  .T1 (delay_T1),  .T2 (d ... "
Module definition of above instance is not found in the design.

This example is from VCS, different simulators will display different messages.



This issue is usually caused due to incorrect Simulation Library Usage. 

The Library B_IOSERDESE2 is part of the SecureIP package and cannot be found in any location (as it is encrypted). 

As a result searches for this Library in our Xilinx Library Folders will return no results.

If you receive this error, please use one of the options below:

  • Use pre-compile simulation libraries - This is a highly recommended approach.
    Run CompXlib (ISE) or compile_simlib (Vivado) targeting your Simulator.
    Once the compiled libraries are generated, ensure that SecureIP is referenced in your library mapping (example -L secureip in Modelsim/Questa)

  • Source the SecureIP fileset at run-time directly.

    (Xilinx Answer 32937)
     provides an example for simulating SecureIP with VCS.
AR# 53635
Date 07/29/2014
Status Active
Type General Article
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