We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 53643

Zynq-7000 SoC PS-DMA Controller - Any DMAFLUSHP that is executed while there is already a flush in progress is merged and ignored


If the DMAFLUSHP is issued twice close together, there is a chance that the Peripheral Request Interface only recognizes one flush request.


You typically would not need to issue two flush instructions back-to-back, so as long as they do not program the peripherals to expect two separate flush requests when there is two flush instructions being issued, there is NO issue.

If there are other DMA peripheral request instructions in between, then there will be two separate flushes.

The DMARMB and DMAWMB will not work around this issue.

IMPORTANT: DO NOT develop the peripheral core expecting two consecutive separate flushes.

AR# 53643
Date 05/21/2013
Status Active
Type Known Issues
  • Zynq-7000
Page Bookmarked