UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 537

XC3000, SYNOPSYS Design Compiler - An example .synopsys_dc.setup file

Description

Keywords: Design Compiler, .synopsys_dc.setup

Urgency: Standard

General Description:
This solution contains an example of a .synopsys_dc.setup file for the Synopsys
Design Compiler (XC3000).

Solution

EXAMPLE DESIGN COMPILER STARTUP FILE - .synopsys_dc.setup
(For XC3000/A/L and XC3100/A/L PARTYPES)

search_path = {. \
<DS401-XACT-Directory>/synopsys/libraries/syn \
<SYNOPSYS-Directory>/libraries/syn}

link_library = {xprim_3020a-6.db xprim_3000a-6.db \
xgen_3000.db xdc_3000a-6.db}

target_library = {xprim_3020a-6.db xprim_3000a-6.db \
xgen_3000.db xdc_3000a-6.db}

symbol_library = xc3000.sdb

define_design_lib WORK -path ./WORK

compile_fix_multiple_port_nets = true

bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
bus_inference_style = "%s<%d>"

edifout_netlist_only = true
edifout_power_and_ground_representation = cell
edifout_write_properties_list = "instance_number port_location part"



AR# 537
Date Created 09/20/1995
Last Updated 04/04/2001
Status Archive
Type General Article