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  3. AR# 5371: 1.5i Virtex PAR - XCV1000 implementation not progressing after 60 hours on 450MHz PC with 384 MB RAM
  4. AR# 53710: MIG 7 Series DDR2 - Why is there a limitation for only 3 ODT ports?

AR# 53710

MIG 7 Series DDR2 - Why is there a limitation for only 3 ODT ports?

Description

The 7 Series FPGAs Memory Interface User Guide (UG586) has the following DDR2 guideline:


For single rank components and DIMMs, the ODT port is repeated based on the number of components. 

The maximum number of allowed ports is 3.

Why is the number of ODT ports limited to 3?

Solution

This requirement was due to an earlier design usage of CKE and ODT which enforced a limit of a maximum of 4 pins of CKE and ODT per bank.

For dual rank devices, this allowed 2 CKE and 2 ODT ports.

Whereas for single rank devices, this allowed a maximum of 3 ODT ports with 1 CKE port.
 
After changing the implementation of CKE and ODT (see Xilinx Answer 45633), the limitation on ODT was not relaxed. 

However, there is no fundamental reason now that 4 ODT ports be used.

Manual changes to support 4 ODT ports can be made.

Please refer to the byte map parameters in table 1-94 of (UG586)

Modify the map parameters to add a 4th ODT. 

If you still have problem generating a 4th ODT, please contact Xilinx Technical Support.

Revision History:
11/19/2014 - Initial Release
AR# 53710
Date 11/20/2014
Status Active
Type Known Issues
Devices
Tools
IP