The 7 Series FPGAs Memory Interface User Guide (UG586) has the following DDR2 guideline:
For single rank components and DIMMs, the ODT port is repeated based on the number of components.
The maximum number of allowed ports is 3.
Why is the number of ODT ports limited to 3?
AR# 53710 | |
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Date | 11/20/2014 |
Status | Active |
Type | Known Issues |
Devices | |
Tools | |
IP |