AR# 53735


LogiCORE IP Aurora 64B/66B - Protocol Enhancement in Channel Initialization Stage


The protocol does not define reception of specific number of IDLE block codes to determine if the channel is ready. Currently, the core declares the remote_ready signal when a single IDLE block code is received from its partner. With the protocol update, Channel Init FSM will look for 8 IDLE block codes before declaring the remote is ready. Apart from this, Channel Init FSM waits for 64 IDLE block codes to be transmitted. These changes will provide more robustness to the core.


Required Changes:

1. <component_name>_sym_dec.v[hd] module changes:

The changes mentioned below applies for both Single lane and multi lane cores.

  i.    Declare remote_ready_cntr as 3-bit counter.

  ii.   Generate remote_ready_det signal with existing REMOTE_READY logic.

  iii.  Increment remote_ready_cntr counter with remote_ready_det signal.

  iv.  Assert REMOTE_READY output when remote_ready_cntr reaches to 3'b111. Modified code snippet shown below:

2. <component_name>_channel_init.v[hd] module changes:

Changes i to iv applies for both single lane and multi lane. Changes required for single lane and multi lane are specified separately for v to vii.

  i.  Declare rx_na_idles_cntr as 4-bit counter.

  ii. Generate rx_na_idles_16d_done internal signal when rx_na_idles_cntr reaches to 4'b1111. Modified code snippet shown below:

  iii.  Declare idle_xmit_cntr as 6-bit counter.

  iv.  Generate txidle_64d_done internal signal when idle_xmit_cntr reaches to 6'b11_1111. Modified code snippet shown below:

  v.  Use this txidle_64d_done signal for state transition from wait_for_remote_r state to ready_r state. Modified code snippet shown below:

Single Lane:


Multi Lane:

vi. Change the condition for condition in present state process block. Modified code snippet shown below:

Single Lane:

Remove the NOT LANE_UP

Multi Lane:

Use (not AND_REDUCE(LANE_UP)) in place of (RESET_CHANNEL or (not OR_REDUCE(LANE_UP))

vii. Change GEN_NA_IDLES as follows: This change applies only for Single Lane and no change required for multi lane cores.


Files to be edited:

1. <component_name>_sym_dec.v[hd] of all lanes

2. <component_name>_channel_init_sm.v[hd] of all lanes

Aurora 64B66B core will be updated with this change in IP release with the 2013.1 Vivado tool. Example files after making the changes mentioned above are attached at the end of this answer record.

Revision History
04/09/2013 - Initial release





Associated Attachments

AR# 53735
Date 04/09/2013
Status Active
Type General Article
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