AR# 53740

Design Advisory for 7 Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature


This Design Advisory Answer Record applies to all of the following cores:

  • 7 Series Integrated Block for PCI Express (v1.8 and earlier versions)
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (v1.4 and earlier versions)
  • AXI Bridge for PCI Express (v1.06.a and earlier versions)

Due to incorrect DRP write access of the GT registers from the wrappers of the cores listed above, it has been found that no clock is output on TXOUTCLK at cold temperature. This issue is caused due to assertion of DRP_WE for multiple clock cycles resulting in spurious writes to GT registers through the DRP ports.

DRP_WE must be enabled for only one clock cycle. This requirement is addressed in (Xilinx Answer 53788).


To prevent this issue from occurring, all customers using the cores listed above must make the following changes in <core_name>_pipe_drp.v and <core_name>_qpll_drp.v files.

assign DRP_WE   = (fsm == FSM_WRITE) || (fsm == FSM_WRDY);

assign DRP_WE   = (fsm == FSM_WRITE);

  • For "7 Series Integrated Block for PCI Express" and "Virtex-7 FPGA Gen3 Integrated Block for PCI Express" cores, these files are located in the 'Source' directory.
  • For "AXI Bridge for PCI Express", in the XPS System Assembly View, right-click on the core and click on 'Make this IP Local'. The tool will copy all files related to the core in the 'pcores' directory. The above two files can be found in the following location:


       If you had created a default design in XPS with v1.06.a core, the name of the corresponding files will be:
                    - axi_pcie_v1_06_a_pcie_7x_v1_6_qpll_drp.v
                    - axi_pcie_v1_06_a_pcie_7x_v1_6_pipe_drp.v 

Revision History
01/21/2013 - Initial release

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AR# 53740
Date 08/26/2013
Status Active
Type Design Advisory