When creating an EDK pcore in System Generator, the vectors within the pcore are configured as Big Endian.
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT s_axi_araddr = araddr, VEC = [0:(32-1)], BUS = S_AXI, DIR = IN
PORT s_axi_arburst = arburst, VEC = [0:(2-1)], BUS = S_AXI, DIR = IN
PORT s_axi_arcache = arcache, VEC = [0:(4-1)], BUS = S_AXI, DIR = IN
PORT s_axi_arid = arid, VEC = [0:(C_S_AXI_ID_WIDTH-1)], BUS = S_AXI, DIR = IN
PORT s_axi_arlen = arlen, VEC = [0:(8-1)], BUS = S_AXI, DIR = IN
This is a known issue with System Generator. It exports EDK pcores as Big Endian. This is due to a legacy in the tools to remain compatible with PLBv4.6 and FSL busses.
To work around this issue, customers who wish to use a System Generator generated pcores in an AXI Little Endian system must manually reverse the orientation of the vector components in HDL, as well as modify the MPD to reflect an EDK generated pcore.
This issue has been fixed in ISE System Generator 14.6, and we recommend using this release.
A patch also exists for Windows 64-bit platforms. See (Xilinx Answer 56214)