Description

I have an EDK design as a sub-module in a PlanAhead project. I would like to prevent XPS from inserting a clock buffer in the clock generator block for the XPS design.

How can I do this?

Solution

To prevent buffers from being added on external ports in EDK projects, open the MHS file and apply the BUFFER_TYPE=none keyword to the external clock port. For reference, see page 19 of the Platform Specification User Guide (UG642).

For example, change the following:

from

PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000

to

PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, BUFFER_TYPE=none, CLK_FREQ = 200000000
PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, BUFFER_TYPE=none, CLK_FREQ = 200000000