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  3. AR# 53779: Design Advisory for Virtex-7 FPGA GTH Transceiver - RX Reset Sequence Requirement for Production Silicon

AR# 53779

Design Advisory for Virtex-7 FPGA GTH Transceiver - RX Reset Sequence Requirement for Production Silicon

Description

This answer record covers the RX reset sequence requirements for the Virtex-7 GTH Transceiver Production Silicon.

Solution

The following sequences for issuing GTRXRESET, RXPMARESET, or RXRATE in the Virtex-7 GTH Production Transceivers must be followed if the GTH transceiver is configured as follows:
 
1. RXOUT_DIV = 2, 4, 8 or 16
AND
2. RX internal data width is 20 or 40-bit (RX_DATA_WIDTH = 20, 40 or 80)
 
For the other modes, this is not required but still supported.
 
These reset sequences can be also used on General ES silicon but are not required. These sequences are implemented in the wrapper generated by 7 Series FPGAs Transceivers Wizard v2.5 in the ISE 14.5/Vivado 2013.1 tool version. The reset sequences are added to v1.9 of the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
 
In these sequences, "user_*" denotes user input. This signal was previously connected directly to the GT primitive. It will now trigger an alternative reset sequence as described below.
"gt_*" denotes connection to GT primitive. The following diagram indicates where this new sequence fits in.
"DRP wr" denotes the function of performing a DRP write to address 9'h011.  The exact DRP transaction is not shown.
 
 
 
 
 
1. GTRXRESET:
 
The following reset sequence must be followed when the user wants to perform GTRXRESET.
 


Steps:
 
  1. User triggers a reset request by asserting user_GTRXRESET.
  2. Set and hold gt_GTRXRESET High. This will cause gt_RXPMARESETDONE to go Low.
  3. Issue DRP write to the GTHE2_CHANNEL primitive, DRP address 9h011, and set bit[11] to 1b0.
    Note: In order to ensure only bit[11] of DRP address 9h011 is modified, it is best to perform a read-modify-write function.
  4. Upon DRP write completion and user_GTRXRESET detected as low, set and hold gt_GTRXRESET low.  If user_GTRXRESET remains asserted upon completion of the DRP write, continue to assert gt_GTRXRESET until user_GTRXRESET is low.
  5. Wait for falling edge of gt_RXPMARESETDONE.
  6. Issue DRP write to the GTHE2_CHANNEL primitive, DRP address 9h011, restoring the original setting for bit[11].  The completion of this DRP write must occur before RXPMARESETDONE switches from low to high.  RXPMARESETDONE will stay low for a minimum of 0.66 us.

Notes: 

  1. Make sure gt_GTRXRESET is output of a register.
  2. Make sure RXPMARESET_TIME is set to 5h3.  This should be the default setting.
  3. The sequence above will only simulate properly if SIM_GTRESET_SPEEDUP is set to FALSE and the GT functional simulation model in unisims library is used.  If SIM_GTRESET_SPEEDUP is set to TRUE or if GT functional simulation model in unifast library is used, the above sequence must be bypassed.
 
2. RXPMARESET:
 
The following reset sequence must be followed when the user wants to perform RXPMARESET.
 
AR53779_2.png

Steps:
 
  1. User triggers a RXPMARESET request by asserting user_RXPMARESET.
  2. Issue DRP write to the GTHE2_CHANNEL primitive, DRP address 9h011, and set bit[11] to 1b0.
    Note: In order to ensure only bit[11] of DRP address 9h011 is modified, it is best to perform a read-modify-write function.
  3. Upon DRP write completion, set and hold gt_RXPMARESET High.
  4. Wait for RXPMARESETDONE to go Low.
  5. Issue DRP write to the GTHE2_CHANNEL primitive, DRP address 9h011, restoring the original setting for bit[11].
  6. Upon DRP write completion and user_RXPMARESET detected as Low, set and hold gt_RXPMARESET Low.  If user_RXPMARESET remains asserted upon completion of the DRP write, continue to assert gt_RXPMARESET until user_RXPMARESET is Low.

Note: Make sure gt_RXPMARESET is output of a register.


3. RXRATE:
 
The following sequence must be followed when the user wants to trigger RX rate change via RXRATE.
 


Steps:
 
  1. User triggers a RX rate change request by changing user_RXRATE.
  2. Issue DRP write to the GTHE2_CHANNEL primitive, DRP address 9h011, and set bit[11] to 1b0.
    Note: In order to ensure only bit[11] of DRP address 9h011 is modified, it is best to perform a read-modify-write function.
  3. Upon DRP write completion, set gt_RXRATE to the value of user_RXRATE.
  4. Wait for RXPMARESETDONE to go Low.
  5. Issue DRP write to the GTHE2_CHANNEL primitive, DRP address 9h011, restoring the original setting for bit[11].  The completion of this DRP write must occur before RXPMARESETDONE switches from Low to High.  RXPMARESETDONE will stay Low for a minimum of 0.66 us.

Notes:

  1. The sequence above will only simulate properly if SIM_GTRESET_SPEEDUP is set to FALSE and the GT functional simulation model in unisims library is used.  If SIM_GTRESET_SPEEDUP is set to TRUE or if GT functional simulation model in unifast library is used, the above sequence must be bypassed.
  2. The steps outlined here for RXRATE change are still being tested and verified on the hardware.

Revision History
04/12/2013 - Updated the user guide version with the reset sequence
02/20/2013 - Updated the beginning to reflect the correct GTH mode combination where the new reset is required
01/31/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54473 LogiCORE IP CPRI Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
42944 Design Advisory Master Answer Record for Virtex-7 FPGA N/A N/A
55445 RXAUI v2.4, 7 Series - Required GTP/GTX and GTH transceiver updates N/A N/A
55446 XAUI v10.4 - 7 Series - Required GTP/GTX and GTH transceiver updates N/A N/A
AR# 53779
Date 04/12/2013
Status Active
Type Design Advisory
Devices
  • Virtex-7
  • Virtex-7 HT

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