Description

Solution

1. Use Internal Vref which allows the Vref pins to be used as normal I/O pins freeing up two pins per bank where inputs are utilized.
   Note: Internal Vref is only an option for data rates below 800 Mb/s. For details, see (Xilinx Answer 42036).
2. Disable Data Mask (DM); Data Mask can be disabled through the 7 Series MIG tool for designs not requiring the ability to mask data. This saves one I/O pin per data byte group (two I/O pins for an x18 interface).
3. Use DCI Cascade to free up two I/O pins (VRN/VRP). Note that the VRN/VRP pins are not within the T* byte groups. Data group signals CANNOT be placed on VRN/VRP. RESET _N can ALWAYS be placed on an available VRN/VRP signal. The remaining Address/Control signals are ONLY allowed on VRN/VRP when ALL of the following conditions are met. Please refer to the Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions User Guide (UG586) for full details.
   • DCI cascade is used.
   • The adjacent byte group (T0/T3) is used as an address/control byte group.
   • An unused pin exists in the adjacent byte group (T0/T3) or the CK output is contained in the adjacent byte group.
4. VRN and VRP signals (or the non-byte group signals in, for example, HR column banks) are the top and bottom signals within a bank. To utilize both VRN and VRP for address/control, place the Address/Control byte groups on T0 and T3 within the bank. This places one address/control byte group adjacent to VRN and the other adjacent to VRP.
5. Drive the input sys_clk pair from a different bank within the same I/O column. For full Clocking Guidelines, see (Xilinx Answer 40603).
   

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