We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 53845

Vivado Implementation - Is there a switch in Vivado that can be used to prevent trimming of unconnected logic?


Is there a switch in the Vivado tool to instruct Implementation to not trim away unconnected logic (similar to the -u MAP switch in ISE)?


This can be done during Vivado logic optimization (opt_design). The opt_design command performs the following optimizations by default:

  • Retarget
  • Constant Propagation
  • Sweep
  • Block RAM Power optimizations

Sweep removes the cells that have no loads. To restrict sweep optimization that is run by default, use the following command in a Vivado Tcl script:

opt_design -retarget -propconst -bram_power_opt

In Project mode, -retarget -propconst -bram_power_opt should be added in the "More Options" field under the "Opt Design (opt_design)" section of the Implementation settings.

For more details, Check the topic "Logic Optimization" in the Vivado Implementation user guide (UG904).


AR# 53845
Date 03/03/2016
Status Active
Type General Article
  • Vivado Design Suite