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AR# 53860

Design Advisory for MIG 7 Series DDR3 - All CK clock pins must to be in the same byte lane/group. Validating Dual Rank Pin-Outs Required.

Description

Starting with the 7 Series FPGAs Memory Interface User Guide v1.6, the following DDR3 SDRAM Design Guideline is included:

  • If multiple CK outputs are used, such as for dual rank, all CK outputs must come from the same byte lane.

This answer record details this pin restriction.  

Important Note: Using the default "New Design" flow, MIG 7 Series has followed this CK pin placement rule since the first officially supported release for dual rank, v1.6. 

However, when using the "Fixed Pin-Out" or "Verify Pin Changes and Update Design" flow, the DRC check against this rule was not included in MIG 7 Series until v1.8 . 

Because of this, when using one of these two flows, incorrect pin-outs may have been verified and generated by MIG 7 Series allowing CK pins to be in separate byte groups. 

Starting with MIG 7 Series v1.8, the correct DRC checks are included. 

All DDR3 Dual Rank MIG 7 series pin-outs should be validated using v1.8.

Solution

Background on CK Pin Requirement:

Characterization of the MIG 7 series solution has shown process variance on the clock outputs across Phaser_OUTs.

This variance can cause set-up/hold violations (tIS/tIH) on Address/Command/Control with respect to CK.

To avoid these violations, the MIG 7 series solutions require all CK outputs to be within the same byte group.

This ensures the same Phaser_OUT creates all interface CK clocks and eliminates potential set-up/hold violations at the SDRAM.

Adherence to this pin rule is strictly required.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
56155 MIG 7 Series - KC705 dual rank example design N/A N/A
AR# 53860
Date Created 01/24/2013
Last Updated 08/15/2014
Status Active
Type Design Advisory
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series