UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 53863: Zynq-7000 SoC ZC706 Evaluation Kit - UG961 (v1.0) SW4 settings to run the BIST on the ZC706

AR# 53863

Zynq-7000 SoC ZC706 Evaluation Kit - UG961 (v1.0) SW4 settings to run the BIST on the ZC706

Description

The Zynq-7000 SoC ZC706 Evaluation Kit Getting Started Guide v1.0 (UG961) (ISE Design Suite 14.3), includes steps to set up the ZC706 board to run the Built-In Self Test (BIST). 

However, (UG961) does not include information on the SW4 settings to run the BIST.

What are the DIP switch settings?

Solution

The ZC706 BIST PDF (XTP242) outlines the steps to follow in order to setup and run the BIST, along with the SW4 settings.

These settings are:

  • SW4 needs to be set to 01 if using the USB Type-A to Micro-B cable provided with the kit, or 10 if using the Platform Cable USB (II) JTAG cable.

The Zynq-7000 SoC ZC706 Evaluation Kit Getting Started Guide v4.0 (UG961) includes these DIP switch settings.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51899 Zynq-7000 SoC ZC706 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 53863
Date 05/16/2018
Status Active
Type General Article
Boards & Kits
  • Zynq-7000 SoC ZC706 Evaluation Kit
Page Bookmarked