AR# 53887


Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - black_box, io_buffer_type, clock_buffer_type, max_fanout


This answer record describes the Vivado Synthesis Attributes below:

(black_box, io_buffer_type, clock_buffer_type, max_fanout)

Coding examples for each attribute are also provided.

The coding examples are attached to this answer record. 

The answer record also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project.

Please refer to the header in each source file for the Synthesis attributes covered in each example.



The black_box attribute is used to direct Vivado Synthesis to not synthesize a specific module within a design.

Vivado will treat this design element as a black box even if valid logic is contained in the module. 

This attribute can be used for debugging purposes.

To apply the attribute:

Verilog Example 

(* black_box *) module test(in1, in2, clk, out1);

VHDL Example

attribute black_box : string;

attribute black_box of beh : architecture is "yes";

Note: In VHDL, setting black_box to "no" does not make it "not" a black box. 

To unset a black box, remove or comment the black_box attribute in HDL.


The io_buffer_type and clock_buffer_type attributes give the user the ability to control the synthesis of buffers applied to any given signal in a design. 

The attributes should be applied on an input or output port in order to describe type of buffer to be used. 

This can be useful when trying to conserve global buffers or when trying to prevent inline buffers while connecting with the IP.

Verilog Example

(* io_buffer_type = "{ibuf | obuf | none}" *)
(* clock_buffer_type = "{bufg | bufh | bufio | bufmr | bufr | none}" *)

VHDL Example

entity test is port(
in1 : std_logic_vector (8 downto 0);
clk : std_logic;
out1 : std_logic_vector(8 downto 0));

attribute io_buffer_type : string;
attribute clock_buffer_type : string;
attribute io_buffer_type of clk : signal is "{ibuf | obuf | none}";
attribute clock_buffer_type of in1 : signal is "{bufg | bufh | bufio | bufmr | bufr | none}";
end test;



The max_fanout attribute applies a limit to the fanout or number of loads driven by a synchronous element. 

Large fanout's on design elements increase the net delays associated with them. 

Reducing the fanout will reduce the net delays of a signal. 

This fanout limitation is accomplished through duplication of a register or driver of a combinatorial signal.

The value of the max_fanout attribute should be an integer equal to the number of loads desired for a particular signal. 

This RTL attribute will override the fanout limit set with the IDE setting -fanout_limit.


Verilog Example 

(* max_fanout = 50 *) reg sig1;

VHDL Example
signal sig1 : std_logic;

attribute max_fanout : integer;
attribute max_fanout of sig1 : signal is 25;

Known Issues:

(Xilinx Answer 51163) - Vivado_Synthesis - MAX_FANOUT Synthesis Attribute not supported for edif netlist files

Table 1:

Attribute Name HDL Files


  • black_box_top.v
  • bb_sub_a.v
  • bb_sub_b.v


  • black_box_top.vhd
  • black_box_sub.vhd
  • buffer_type.v
  • buffer_type.vhd
  • max_fanout.v
  • max_fanout.vhd


Associated Attachments

Name File Size File Type 658 Bytes ZIP 914 Bytes ZIP 1 KB ZIP 45 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
55160 Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support N/A N/A
AR# 53887
Date 06/04/2014
Status Active
Type Solution Center
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