You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
7 Series - When the Readback CRC and AES bitstream encryption features are both enabled, the Readback CRC requires the ICAP to be included in the design to function.
When the Readback CRC (POST_CRC) and AES bitstream encryption features are both enabled, the Readback CRC will not be operational unless the ICAP is instantiated and a clock is provided.
Software prior to ISE Design Suite 14.5 and Vivado Design Suite 2013.1 will not catch this limitation.
Was this Answer Record helpful?