Version Found: v1.8
Version Resolved and other Known Issues: See (Xilinx Answer 45195)
7 series architecture requires that for given byte lane, the DQSCC_N location is used to generate the 3-state control signal. RLDRAM II designs require that the DQSCC_N location in the same byte lane as data must be unused or can be shared with QVLD, DK#, or DM. This requirement is met by MIG 7 series v1.8 when using the Create Design flow and Pin/Bank Selection Mode shown below:
However, when using the "Fixed Pin Out" mode or the "Verify Pin Changes and Update Design" flow, users must ensure this requirement is met manually as the violation is not detected properly using these flows.
If this pinout requirement is not met, designs will fail in both behavioral simulation and hardware simulations during calibration, and, as a result, the 3-state control for the bi-directional data bits will not function properly.
There is no workaround available, as the DQSCC_N location for 3-state control is a dedicated route in the 7 series architecture. The pinout requirement must be met.
01/24/2012 - Initial Release